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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13742-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90980 Series MB90982/MB90F983/MB90V485B
DESCRIPTION
The MB90980 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90980 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up/down-counter, PWC timer, I2C*2 interface, DTP/ external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C standard Specification as defined by Philips.
FEATURES
* Clock * Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied x 4 (25 MHz internal operating frequency/3.3 V 0.3 V) 62.5 ns/4 MHz base frequency multiplied x 4 (16 MHz internal operating frequency/3.0 V 0.3 V) PLL clock multiplier (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://jp.fujitsu.com/microelectronics/products/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006 FUJITSU LIMITED All rights reserved
MB90980 Series
(Continued) * Maximum memory space * 16 Mbytes * Instruction set optimized for controller applications * Supported data types (bit, byte, word, or long word) * Typical addressing modes (23 types) * Enhanced signed multiplication/division instruction and RETI instruction functions * 32-bit accumulator for enhanced high-precision calculation * Instruction set designed for high-level language (C) and multi-task operations * System stack pointer adopted * Instruction set compatibility and barrel shift instructions * Enhanced execution speed * 4 byte instruction queue * Enhanced interrupt functions * 8 levels setting with programmable priority, 8 external interrupt pins * Data transmission function (DMAC) * Up to 16 channels * Embedded ROM * Flash versions : 192 Kbytes, Mask versions : 128 Kbytes * Embedded RAM * Flash versions : 12 Kbytes, Mask versions : 10 Kbytes * General purpose ports * Up to 48 ports (10 ports with output open-drain settings) * 8/10-bit A/D converter * 8-channel RC sequential comparison type (10-bit resolution, 3.68 s conversion time (at 25 MHz) ) * I2C interface * 1 channel, P76/P77 N-ch open drain pin (without P-ch) * UART * 1 channel * Extended I/O serial interface (SIO) * 2 channels * 8/16-bit PPG * 2 channels (with 8-bit x 4 channels/16-bit x 2 channels mode switching function) * 8/16-bit up/down timer * 1 channel (with 8-bit x 2 channels/16-bit x 1-channel mode switching function) * 16-bit PWC * 2 channels (Capable of compare the inputs) * 16-bit reload timer * 1 channel * 16-bit I/O timer * 2 channels input capture, 4 channels output compare, 1 channel free run timer * On chip dual clock generator system * Low-power consumption (standby) mode * With stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode
2
MB90980 Series
* Packages * LQFP 64 * Process * CMOS technology * Power supply voltage 3 V, single source (some ports can be operated by 5 V power supply.)
3
MB90980 Series
PRODUCT LINEUP
Part number Item Classification ROM size RAM size MB90982 MB90F983 MB90V485B
Mask ROM product Flash memory product Evaluation product 128 Kbytes 192 Kbytes 10 Kbytes 12 Kbytes 16 Kbytes Number of instructions : 351 Instruction bit length : 8-bit, 16-bit CPU function Instruction length : 1 byte to 7 bytes Data bit length : 1-bit, 8-bits, 16-bits Minimum execution time : 40 ns (25 MHz machine clock) General-purpose I/O ports: up to 48 General-purpose I/O ports (CMOS output) Ports General-purpose I/O ports (with pull-up resistance Input) General-purpose I/O ports (N-ch open drain output) UART 1 channel, start-stop synchronized 8-bit x 6 channels/ 8/16-bit PPG 8-bit x 4 channels/16-bit x 2 channels 16-bit x 3 channels 8/16-bit up/down 6 event input pins, 8-bit up/down counters : 2 counter/timer 8-bit reload/compare registers : 2 16-bit free run Number of channels : 1 timer Overflow interrupt Number of channels : 6 16-bit Output compare Number of channels : 4 Pin input factor : A match I/O timers (OCU) Pin input factor : A match signal of compare register signal of compare register Input capture Number of channels : 2 (ICU) Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt channels : 8 (edge or level detection) Extended I/O serial interface 2 channels, embedded 1 channel I2C interface*2 PWC 2 channels 3 channels 18-bit counter Timebase timer Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) Conversion resolution : 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, A/D converter programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms Watchdog timer (minimum value, at 4 MHz base oscillator) Low-power consumption Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer (standby) modes mode Process CMOS Mask model 3V/5V Flash model 3V/5V 3V/5V power supply*1 Type power supply*1 power supply*1 Emulator power supply*3 Yes (Continued)
4
MB90980 Series
(Continued) *1 : 3V/5V I/F pin : All pins should be for 3 V power supply without P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, and P77. *2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I2C. *3 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the hardware manual of MB2147-01 or MB2147-20 ("3.3 Emulator-dedicated Power Supply Switching") about details. Note : Ensure that you must write to Flash at VCC = 3.13 V to 3.60 V (3.3 V + 10%, -5%) .
5
MB90980 Series
PIN ASSIGNMENT
(TOP VIEW)
P80/IRQ0
P81/IRQ1
P82/IRQ2
P83/IRQ3
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVSS
RST
X0A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AVCC AVRH P27/PPG3 P26/PPG2 P25/PPG1 P24/PPG0 P37/PWC1 P36/PWC0 P35/ZIN1 P34/BIN1 P33/AIN1 P32/ZIN0 P31/BIN0 P30/AIN0 P42/SCK2 VCC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X1A
VSS X1 X0 MOD2 MOD1 MOD0 P84/IRQ4 P85/IRQ5 P86/IRQ6 P87/IRQ7 P90/SIN1 P91/SOT1 P92/SCK1 P93/FRCK/ADTG P96/IN0 VSS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P97/IN1
P72/SCK0
P40/SIN2
P74/TOT0
P41/SOT2
P73/TIN0
P77/SDA
P76/SCL
VSS
P71/SOT0
P70/SIN0
PA3/OUT3
PA2/OUT2
PA1/OUT1
PA0/OUT0
(FPT-64P-M03) Notes : * I2C pin P76 and P77 are N-ch open drain pin (without P-ch) . * P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 also used as 3 V/5 V I/F pin.
6
VCC3
32
MB90980 Series
PIN DESCRIPTIONS
Pin No. 46 47 50 49 51 3 to 6 14 13 12 11 10 9 7, 8 19 18 15 60 to 63 56 to 59 26 25 Pin name X0 X1 X0A X1A RST P27 to P24 PPG3 to PPG0 P30 AIN0 P31 BIN0 P32 ZIN0 P33 AIN1 P34 BIN1 P35 ZIN1 P37, P36 PWC1, PWC0 P40 SIN2 P41 SOT2 P42 SCK2 P63 to P60 AN3 to AN0 P67 to P64 AN7 to AN4 P70 SIN0 P71 SOT0 I/O Circuit type* A A A A B E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) G (CMOS/H) F (CMOS) G (CMOS/H) H (CMOS) F (CMOS) G (CMOS/H) F (CMOS) Oscillator pin Oscillator pin 32 kHz oscillator pin 32 kHz oscillator pin Reset input pin General purpose I/O port PPG timer output pin General purpose I/O port 8/16-bit up/down timer counter input pin (ch.0) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.0) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.0) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.1) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.1) General purpose I/O port 8/16-bit up/down timer counter input pin (ch.1) General purpose I/O port PWC input pin General purpose I/O port Simple serial I/O 2-input pin General purpose I/O port Simple serial I/O 2-output pin General purpose I/O port Simple serial I/O 2-clock I/O pin General purpose I/O port Analog input pin General purpose I/O port Analog input pin General purpose I/O port UART data input pin General purpose I/O port UART data output pin (Continued) Function
7
MB90980 Series
Pin No. 24 23 22
Pin name P72 SCK0 P73 TIN0 P74 TOT0 P76
I/O Circuit type* G (CMOS/H) G (CMOS/H) F (CMOS) I (NMOS/H) I (NMOS/H) E (CMOS/H) E (CMOS/H) E (CMOS/H) D (CMOS) E (CMOS/H) General purpose I/O port UART clock I/O pin General purpose I/O port
Function
16-bit reload timer event input pin General purpose I/O port 16-bit reload timer output pin General purpose I/O port This pin functions as the I2C interface clock I/O pin. Set port output to Hi-Z during the I2C interface operation. General purpose I/O port This pin functions as the I2C interface data I/O pin. Set port output to Hi-Z during the I2C interface operation. General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port Simple serial I/O1-data input pin General purpose I/O port Simple serial I/O-1 data output pin General purpose I/O port Simple serial I/O-1 data I/O pin General purpose I/O port When using free-run timer, this pin functions as the external clock input pin. When using A/D converter, this pin fuctions as the external trigger input pin.
21
SCL P77
20
SDA P83 to P80 IRQ3 to IRQ0 P87 to P84 IRQ7 to IRQ4 P90 SIN1 P91 SOT1 P92 SCK1 P93
52 to 55 39 to 42 38 37 36
35
FRCK ADTG
E (CMOS/H)
34 31 27 to 30 1 2 64 43 to 45 32 8
P96 IN0 P97 IN1 PA3 to PA0 OUT3 to OUT0 AVCC AVRH AVSS MD0 to MD2 VCC3
E (CMOS/H) E (CMOS/H) D (CMOS) J (CMOS/H)
General purpose I/O port Input capture ch.0 trigger input pin General purpose I/O port Input capture ch.1 trigger input pin General purpose I/O port Output compare event output pin A/D converter power supply pin A/D converter external reference power supply pin A/D converter power supply pin Operating mode selection input pins 3.3 V 0.3 V power supply pins (VCC3) (Continued)
MB90980 Series
(Continued) Pin No. Pin name I/O Circuit type* Function 3 V/5 V power supply pin. 5 V power supply pin when P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 are used as 5 V I/F pins. Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . Power supply input pins (GND)
16
VCC5
17, 33, 48
VSS
* : Refer to " I/O CIRCUIT TYPES" for I/O circuit types.
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MB90980 Series
I/O CIRCUIT TYPES
Type
X1, X1A
Circuit
Remarks * Oscillator feedback resistance X1, X0 : approx. 1 M X1A, X0A : approx. 10 M * With standby control
X0, X0A
A
Hard/soft standby control signal Hysteresis input with pull-up resistance B
HYS
CTL P-ch P-ch
* With input pull-up resistance control * CMOS level input/output
C
N-ch
CMOS
Standby control signal CMOS level input/output
P-ch
N-ch
D
CMOS
Standby control signal * Hysteresis input * CMOS level output
P-ch
N-ch
E
CMOS
Standby control signal (Continued)
10
MB90980 Series
(Continued) Type
Circuit
P-ch
Remarks * CMOS level input/output * With open drain control
Open drain control signal
N-ch
F
CMOS
Standby control signal
P-ch
Open drain control signal
* CMOS level output * Hysteresis input * With open drain control
N-ch
G
Standby control signal
P-ch
* CMOS level input/output * Analog input
N-ch
H
CMOS
Standby control signal Analog input * Hysteresis input * N-ch open drain output
Digital output I HYS Standby control signal Flash memory model
* CMOS level input * With high voltage control for flash testing
Control signal J Mode input Diffusion resistance Mask ROM model Hysteresis input 11 Hysteresis input
MB90980 Series
CAUTION OF USING DEVICES
1. Maximum rated voltages (preventing latchup)
In CMOS IC devices, a condition known as latchup may occur if voltages higher than VCC or lower than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS exceeds the rated voltage level. When latchup occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) .
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latchup, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins.
3. Notes on Using External Clock
Even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals.
X0
OPEN
X1
4. Treatment of Power Supply Pins (VCC/VSS)
When multiple VCC pins or VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal storobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC pin or VSS pin of this device with as low impedane as possible. It is also recommended that a bypass capacitor of approximately 0.1 F be placed between the VCC and VSS lines as close to this device as possible.
5. Crystal Oscillator Circuits
Noise around the high-speed oscillation pins (X0 and X1) and low-speed oscillation pins (X0A and X1A) may cause this device to operate abnormally. Design the printed circuit board so that the crystal oscillator (or ceramic oscillator) and bypass capacitor to the ground are located as close to the high-speed oscillation pins and lowspeed oscillation pins as possible. Also, design the printed circuit board to prevent the wiring from crossing another writing. It is highly recommended to provide a printed circuit board artwork surrounding the high-speed oscillation pins and low-speed oscillation pins with a ground area for stabilizing the operation.
12
MB90980 Series
6. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
7. Proper power-on/off sequence
The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC.
8. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS.
9. Precautions when turning the power supply on
In order to prevent abnormal operation in the chip's internal step-down circuits, a voltage rise time during poweron of 50 s (0.2 V to 2.7 V) or greater should be assured.
10. Supply Voltage Stabilization
Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50 Hz/60 Hz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off.
11. Notes on Using Power Supply
Only the MB90980 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P24 to P27, P30 to P37, P40 to P42 and P70 to P74, P76, P77 can be intefaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies.
12. Treatment of NC pins
NC (internally connected) pins should always be left open.
13. Writing to Flash memory
For serial writing to Flash memory, always ensure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to Flash memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V.
13
MB90980 Series
BLOCK DIAGRAM
X0, X1, RST X0A, X1A MD2, MD1, MD0 8
Clock control Circuit
RAM
CPU F2MC16LX series core
Interrupt controller
ROM
2
8/16-bit PPG
PPG0, PPG1 PPG2, PPG3
2
Communication prescaler
2
8/16-bit up/down counter
F2MC-16LX Bus
2 2 2
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 2 2 2
UART
Input/output timer 16-bit input capture x
2 channels 2 4 IN0, IN1 OUT0, OUT1, OUT2, OUT3,
Extended I/O serial interface x 2 channels
16-bit output compare x 4 channels 16-bit free-run timer
AVCC AVRH AVSS ADTG AN0 to AN7
16-bit reload timer A/D converter ( 8/10-bit ) I2C interface
TIN0 TOT0
8
SCL SDA
PWC0 PWC1
External interrupt PWC x 2 channels
8
IRQ0 to IRQ7
I/O port
4 P24 8 P30 3 P40 8 P60 5 P70 2 P76, P77 8 P80 4 P90 2 P96, P97 4 PA0
to
P27
to
P37
to
P42
to
P67
to
P74
to
P87
to
P93
to
PA3
P40 to P42 ( x 3) : with an open drain setting register I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port.
14
MB90980 Series
MEMORY MAP
Single chip
FFFFFFH
ROM area Address #1
FC0000H 010000H ROM area, Image of FF bank Address #2
Address #3
RAM 000100H 0000D0H
Register
Peripheral 000000H Internal access No access
Model MB90F983
Address #1 FC0000H *1
Address #2
Address #3 003100H 002900H
004000H or 008000H, selected by the MS bit in MB90982 FD0000H*2 the ROMM register *1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH.
*2 : No memory cells from FE0000H to FEFFFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank is the same, enabling reference to tables in ROM without the "far" pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to "0", the ROM area in the FF bank will exceed 48 Kbytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only.
15
MB90980 Series
F2MC-16LX CPU PROGRAMMING MODEL
*Dedicated registers
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program counter bank register Data bank register User stack bank register System stack bank register Additional data bank register
*General purpose registers
MSB 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16-bit LSB
*Processor status
bit 15 PS ILM bit 13 bit 12 RP bit 8 bit 7 CCR bit 0
16
MB90980 Series
I/O MAP
Abbreviated Address register name 000000H, 000001H PDR2 000002H 000003H PDR3 000004H PDR4 000005H PDR6 000006H 000007H PDR7 000008H PDR8 000009H PDR9 00000AH PDRA
Register name
R/W Reserved area
Resource name
Initial value
Port 2 data register Port 3 data register Port 4 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register
R/W R/W R/W Reserved area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Port 2 Port 3 Port 4 Port 6 Port 7 Port 8 Port 9 Port A Up/down timer input control DTP/external interrupts
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 11XXXXXXB XXXXXXXXB XXXXXXXXB - - - - XXXXB XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
00000BH 00000CH 00000DH 00000EH 00000FH 000010H, 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH, 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H
UDER ENIR EIRR ELVR
Up/down timer input enable register Interrupt/DTP enable register Interrupt/DTP source register Request level setting register Request level setting register
Reserved area DDR2 DDR3 DDR4 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 Port 2 direction register Port 3 direction register Port 4 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register R/W R/W R/W Reserved area R/W R/W R/W R/W R/W R/W Reserved area ODR7 ADER SMR Port 7 output pin register Analog input enable register Serial mode register R/W Port 7 (Open-drain control) Port 6, A/D XXX 0 0 0 0 0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 X 0 0B 0 0 0 0 0 1 0 0B UART XXXXXXXXB 0 0 0 0 1 0 0 0B Communication prescaler (UART) Port 2 Port 3 Port 4 Port 6 Port 7 Port 8 Port 9 Port A Port 4 (Open-drain control) 0 0 0 0 XXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 XX 0 0 0 0B - - - - 0 0 0 0B XXXXX 0 0 0B
R/W R/W W, SCR Serial control register R/W SIDR/SODR Serial input/output register R/W R, SSR Serial status register R/W Reserved area Communication prescaler control CDCR R/W register
0 0 - - 0 0 0 0B (Continued) 17
MB90980 Series
Abbreviated Address register name Register name SMCS0 Serial mode control status register 0 000026H 000027H SMCS0 Serial mode control status register 0 000028H SDR0 Serial data register 0
R/W R, R/W R, R/W R/W R/W R, R/W R, R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name SIO1 (ch.0) Communication prescaler SIO1 (ch.0) SIO2 (ch.1) Communication prescaler SIO2 (ch.1)
Initial value - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0 - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H to 000039H 00003AH 00003BH 00003CH 00003DH 00003EH, 00003FH 000040H 000041H 000042H 000043H to 000045H 000046H 000047H 000048H 000049H
SDCR0 SMCS1 SMCS1 SDR1 SDCR1 PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3
Communication prescaler control register 0 Serial mode control status register 1 Serial mode control status register 1 Serial data register 1 Communication prescaler control register 1 Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload register H (ch.1) Reload register L (ch.2) Reload register H (ch.2) Reload register L (ch.3) Reload register H (ch.3)
8/16-bit PPG (ch.0 to ch.3)
Reserved area PPGC0 PPGC1 PPGC2 PPGC3 PPG0 operating mode control register PPG1 operating mode control register PPG2 operating mode control register PPG3 operating mode control register R/W R/W R/W R/W 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B 0 X 0 0 0XX 1B 0 X 0 0 0 0 0 1B
8/16-bit PPG (ch.0 to ch.3)
Reserved area PPG01 PPG23 PPG0, PPG1 output control register R/W Reserved area PPG2, PPG3 output control register R/W Reserved area ADCS1 ADCS2 ADCR1 ADCR2 Control status register Data register R/W W, R/W R W, R 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 XXXB (Continued) 8/16-bit PPG 8/16-bit PPG 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
8/10-bit A/D converter
18
MB90980 Series
Abbreviated Address register name Register name 00004AH Output compare register (ch.0) lower digits OCCP0 00004BH Output compare register (ch.0) upper digits
R/W R/W R/W R/W R/W
Resource name
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H to 000055H 000056H
OCCP1 OCCP2 OCCP3
Output compare register (ch.1) lower digits Output compare register (ch.1) upper digits Output compare register (ch.2) lower digits Output compare register (ch.2) upper digits Output compare register (ch.3) lower digits Output compare register (ch.3) upper digits Reserved area Output compare control register (ch.0, ch.1) lower digits Output compare control register (ch.0, ch.1) upper digits Output compare control register (ch.2, ch.3) lower digits Output compare control register (ch.2, ch.3) upper digits Reserved area
0 0 0 0 0 0 0 0B 16-bit I/O timer 0 0 0 0 0 0 0 0B output compare (ch.0 to ch.3) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
R/W R/W R/W R/W
0 0 0 0 - - 0 0B 16-bit I/O timer - - - 0 0 0 0 0B output compare (ch.0 to ch.3) 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B
OCS01 000057H 000058H OCS23 000059H 00005AH, 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH TCDT TCDT TCCS TCCS CPCLR UDCR0 UDCR1 RCR0 RCR1 CCRL0 CCRH0 IPCP0 IPCP1 ICS01
Input capture data register (ch.0) lower digits Input capture data register (ch.0) upper digits Input capture data register (ch.1) lower digits Input capture data register (ch.1) upper digits Input capture control status register Reserved area Timer counter data register lower digits Timer counter data register upper digits Timer counter control status register Timer counter control status register Compare clear register lower digits Compare clear register upper digits Up/down count register (ch.0) Up/down count register (ch.1) Reload/compare register (ch.0) Reload/compare register (ch.1) Counter control register (ch.0) lower digits Counter control register (ch.0) upper digits
R R R R R/W R/W R/W R/W R/W R/W R R W W W, R/W R/W 8/16-bit up/ down counter/ timer 16-bit I/O timer input capture (ch.0, ch.1)
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit I/O timer 0 0 0 0 0 0 0 0B free-run timer 0 - - 0 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 X 0 0 X 0 0 0B 0 0 0 0 0 0 0 0B (Continued)
19
MB90980 Series
Abbreviated Address register name
Register name
R/W Reserved area
Resource name ROM mirroring function 8/16-bit up/down counter/timer
Initial value
00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH to 000081H 000082H 000083H 000084H 000085H to 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH, 00008EH 00008FH to 00009BH 00009CH 00009DH 00009EH 00009FH ROMM CCRL1 CCRH1 CSR0 CSR1
ROM mirror function select register
R/W
- - - - - - 0 1B 0 X 0 0 X 0 0 0B - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
Counter control register (ch.1) R/W lower digits Counter control register (ch.1) R/W upper digits Counter status register (ch.0) R/W Reserved area Counter status register (ch.1) R, R/W Reserved area PWC control/status register PWC data buffer register PWC control/status register PWC data buffer register R, R/W
8/16-bit UDC
0 0 0 0 0 0 0 0B
PWCSR0 PWCR0 PWCSR1 PWCR1
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB PWC timer (ch.0) 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R, R/W 0 0 0 0 0 0 0 XB PWC timer (ch. 1) 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B Reserved area
DIVR0 DIVR1
R/W Reserved area Dividing ratio control register R/W Reserved area
Dividing ratio control register
PWC (ch.0) PWC (ch.1)
- - - - - - 0 0B - - - - - - 0 0B
IBSR IBCR ICCR IADR IDAR
Bus status register Bus control register Clock control register Address register Data register
R R/W R/W R/W R/W Reserved area Disabled
I2C
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0 X X X X XB - X X X X X X XB XXXXXXXXB
DSRL DSRH PACSR DIRR
DMAC status register DMAC status register Program address detection control status resister Dilayed interrupt source generator/ cancel register
R/W R/W R/W R/W
DMAC 0 0 0 0 0 0 0 0B DMAC 0 0 0 0 0 0 0 0B Address match 0 0 0 0 0 0 0 0B detection function Delayed interruput - - - - - - - 0B generator module (Continued)
20
MB90980 Series
Abbreviated Address register name
Register name Low-power consumption mode control register Clock select register
R/W W, R/W R, R/W Reserved area
Resource name Low-power operation Low-power operation
Initial value 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH
LPMCR CKSCR
WDTC TBTC WTC DERL DERH FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
Watchdog timer control register Timebase timer control register Watch timer control register DMAC enable register DMAC enable register Flash memory control status register Disabled Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15
R, W W, R/W R, R/W
Watchdog timer Timebase timer Watch timer DMAC DMAC
XXXXX 1 1 1B 1 X X 0 0 1 0 0B 1 0 0 0 1 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
Reserved area R/W R/W
W, R/W Flash memory I/F 0 0 0 X 0 0 0 0B W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Reserved area TMCSR
TMR/TMRLR
Timer control status register 16-bit timer register/ 16-bit reload register
R/W 16-bit reload timer R/W Reserved area
0 0 0 0 0 0 0 0B - - - - 0 0 0 0B XXXXXXXXB
(Continued)
21
MB90980 Series
(Continued)
Abbreviated Address register name
Register name PLL output select register External area
R/W W
Resource name Low-power operation
Initial value - - - - - - 0 0B
0000CFH 0000D0H to 0000FFH 000100H to 00000#H 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H
PLLOS
RAM area Program address detection resister 0 (Low order address) PADR0 Program address detection resister 0 (Middle order address) Program address detection resister 0 (High order address) Program address detection resister 1 (Low order address) PADR1 Program address detection resister 1 (Middle order address) Program address detection resister 1 (High order address) R/W Address match detection function XXXXXXXXB R/W Address match detection function XXXXXXXXB
Notes : * Descriptions for R/W R/W : Enabled to read and write R : Read only W : Write only * Descriptions for initial value 0 : The initila value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. : This bit is not used.
22
MB90980 Series
INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception INT0 (IRQ0) INT1 (IRQ1) INT2 (IRQ2) INT3 (IRQ3) INT4 (IRQ4) INT5 (IRQ5) INT6 (IRQ6) INT7 (IRQ7) PWC1 PWC0 PPG0/PPG1 counter borrow PPG2/PPG3 counter borrow 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/inversion Input capture (ch.0) load Input capture (ch.1) load Output compare (ch.0) match Output compare (ch.1) match Output compare (ch.2) match Output compare (ch.3) match UART sending completed 16-bit free run timer overflow, 16-bit reload timer underflow*2 UART receiving compleated SIO1 (ch.0) SIO2 (ch.1) x x Clear of EI2OS x x x DMAC cnannel number 0 x x x x x x x x
1 2 3
Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H
Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H
x 5 6 8 9 10 x 11 12 7 13 14
ICR07
0000B7H
ICR08 ICR09 ICR10 ICR11
0000B8H 0000B9H 0000BAH 0000BBH
ICR12
0000BCH
ICR13
0000BDH (Continued)
23
MB90980 Series
(Continued) Interrupt source I2C interface 8/10-bit A/D converter Flash write/erase, timebase timer,watch timer *1 Delay interrupt generator module x x Clear of EI2OS x DMAC channel number x 15 x x Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H ICR15 FFFF54H 0000BFH Interrupt control register Number ICR14 Address 0000BEH
x : Interrupt request flag is not cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal. : Interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : Caution : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time. *2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable (TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to IL0 : 111B) , then set the INTE bit to 0. Note : If there are two interrupt sources for the same interrupt number, the interrupt request flags of both resources are cleared by the EI2OS/DMAC. Therefore if either of the two sources uses the EI2OS/DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the resource that does not use the EI2OS/DMAC function should be set to "0" and the interrupt function should be handled by software polling.
24
MB90980 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC3 Power supply voltage*1 VCC5 AVCC AVRH Input voltage*1 Output volatage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level total average output current Power consumption Operating temperature Storage temperature VI VO ICLAMP ICLAMP IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -2.0 -40 -55 Max VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 +2.0 20 10 3 60 30 -10 -3 -60 -30 320 +85 +150 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *6 *6 *4 *5 *3 *3, *8, *9 *3 *3, *8, *9 *7 *7 *4 *5 *2 Remarks
*1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : V1 and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Maximum output current is defined as the peak value for one of the corresponding pins. *5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *7 : * Applicable to pins : P24 to P27, P30 to P37, P40 to P42, P60 to P67, P70 to P74, P76, P77, P80 to P87, P90 to P93, P96, P97, PA0 to PA3 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 25
MB90980 Series
* Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: * Input/Output Equivalent circuits Protective diode Limiting resistance
VCC P-ch
+B input (0 V to 16 V)
N-ch
R
*8 : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. P76 and P77 is N-ch open drain pin. *9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (VCC3 = VCC5) , the ratings are applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB90980 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC3 Supply voltage VCC5 VIH VIH2 "H" level input voltage VIHS VIHM VIHX VIL "L" level input voltage VILS VILM VILX Operating temperature TA Value Min 2.7 1.8 2.7 1.8 0.7 VCC 0.7 VCC 0.8 VCC VCC - 0.3 0.8 VCC VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 Max 3.6 3.6 5.5 5.5 VCC + 0.3 VSS + 5.8 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.1 +85 Unit V V V V V V V V V V V V V C Remarks During normal operation To maintain RAM state in stop mode During normal operation* To maintain RAM state in stop mode* All pins other than VIH2, VIHS, VIHM and VIHX P76, P77 pins (N-ch open drain pins) Hysteresis input pins MD pin input X0A pin, X1A pin All pins other than VILS, VILM and VIHX Hysteresis input pins MD pin input X0A pin, X1A pin
* : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
27
MB90980 Series
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Condition VCC = 2.7 V, IOH = -1.6 mA VCC = 4.5 V, IOH = -4.0 mA VCC = 2.7 V, IOL = 2.0 mA VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, VSS < VI < VCC VCC = 3.0 V, at TA = +25 C At VCC = 3.3 V, internal 25 MHz operation, normal operation At VCC = 3.3 V, internal 25 MHz operation, Flash programming At VCC = 3.3 V, internal 25 MHz operation, sleep mode At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, sub clock operation (TA = +25 C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, watch mode (TA = +25 C) TA = +25 C, stop mode, at VCC = 3.3 V Min Value Typ 53 0.1 Max 0.4 0.4 +10 200 10 Unit V V V V A k A At using 5 V power supply At using 5 V power supply
Remarks
"H" level output voltage
VOH
All output pins
VCC3 - 0.3 VCC5 - 0.5 -10 20
"L" level output voltage Input leakage current Pull-up resistance Open drain output current
VOL
All output pins All input pins P40 to P42, P70 to P74, P76, P77
IIL RPULL Ileak
45
60
mA
ICC
55
70
mA
ICCS Power supply current ICCL
17
35
mA
15
140
A
ICCT
Other than AVCC, AVSS, VCC, VSS

1.8
40
A A pF
ICCH Input capacitance CIN
0.8 5
40 15
Notes : * Pins P40 to P42, P70 to P74, P76, and P77 are N-ch open drain pins with control, which are usually used as CMOS. * P76 and P77 are open drain pins without P-ch. * For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. * When the device is used with dual power supplies, P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.
28
MB90980 Series
4. AC Characteristics
(1) Clock Timing (VSS = 0.0 V, TA = -40 C to +85 C) Parameter SymPin name bol Condition Clock frequency FCH X0, X1 FCL Clock cycle time tC tCL PWH PWL PWLH PWLL tcr tcf fCP fCPL tCP tCPL X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min 3 3 4 3 3 3 3 3 20 5 1.5 40.0 Typ 32.768 30.5 15.2 8.192 122.1 Max 25 50 25 12.5 6.66 6.25 4.16 3.12 333 5 25 666 kHz ns s ns s ns *2 With external clock *1 Unit Remarks External crystal oscillator External clock input 1 multiplied PLL MHz 2 multiplied PLL 3 multiplied PLL 4 multiplied PLL 6 multiplied PLL 8 multiplied PLL
Input clock pulse width
Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time
MHz *1 kHz ns s *1
*1 : Be careful of the operating voltage. *2 : Duty raito should be 50 % 3 %.
29
MB90980 Series
* X0, X1 clock timing
tC
X0
PWH tcf PWL tcr
0.8 VCC 0.2 VCC
* X0A, X1A clock timing
tCL
X0A
PWLH tcf PWLL tcr
0.8 VCC 0.1 V
30
MB90980 Series
* Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage
3.6 Range of warranted PLL operation 3.0 2.7 Normal operating range
Supply voltage VCC (V)
1.5
4
16
25
Internal clock fCP (MHz) Notes: * Only at 1 multiplied PLL, use with more than fCP = 4 MHz. * For A/D operating frequency, refer to "5. A/D Converter Electrical Characteristics". Base oscillator frequency vs. Internal operating clock frequency
25 24
x 8*3 x 6*3 x 3*1 x 2*1,*2 x4 *1,*2 x 1*1 No multiplied
Internal clock fCP (MHz)
20 18 16 12 9 8 6 4 1.5
3 4 5 6 8 10 12.5
16
20
25
32
40
50
Base oscillator clock FCH (MHz) *1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP 25 MHz, set the PLLOS register to "DIV2 bit = 1" and "PLL2 bit = 1". [Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "0" PLLOS register : DIV2 bit = "1", PLL2 bit = "1" [Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "0" PLLOS register : DIV2 bit = "1", PLL2 bit = "1" *2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP 25 MHz, the following setting is also enabled. 2 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "0" PLLOS register : DIV2 bit = "0", PLL2 bit = "1" 4 multiplied PLL : CKSCR register : CS1 bit = "0", CS0 bit = "1" PLLOS register : DIV2 bit = "0", PLL2 bit = "1" *3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to "DIV2 bit = 0" and "PLL2 bit = 1". [Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "0" PLLOS register : DIV2 bit = "0", PLL2 bit = "1" [Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL : CKSCR register : CS1 bit = "1", CS0 bit = "1" PLLOS register : DIV2 bit = "0", PLL2 bit = "1" 31
MB90980 Series
AC standards are set at the following measurement voltage values. * Input signal waveform Hysteresis input pins
0.8 VCC 0.2 VCC
* Output signal waveform Output pins
2.4 V 0.8 V
* Pins other than hysteresis input/MD input
0.7 VCC 0.3 VCC
32
MB90980 Series
(2) Reset Input Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Conditions Value Min 16 tCP*1 Reset input time tRSTL RST Oscillator oscillation time*2 + 4 tCP*1 Max Unit ns ms Remarks Normal operation Stop mode
*1 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". *2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a FAR/ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. * In stop mode
tRSTL RST
0.2 Vcc 0.2 Vcc
X0
90 % of amplitude
Internal operating clock
Oscillator oscillation time
4 tCP
Oscillator stabilization wait time
Instruction execution Internal reset
33
MB90980 Series
(3) Power-on Reset Standards (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Power rise time Power down time Symbol tR tOFF Pin name Conditions VCC VCC Value Min 1 Max 30 Unit ms ms * In repeated operation Remarks
* : Power rise time requires VCC < 0.2 V. Notes: * The above standards are for the application of a power-on reset. * Within the device, the power-on reset should be applied by switching the power supply off and on again.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied.
Main power supply voltage VCC Sub power supply voltage
VSS
RAM data maintenance
The slope of voltage increase should be kept within 50 mV/ms.
34
MB90980 Series
(4) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 -80 -120 100 200 tCP*2 4 tCP* 4 tCP* 60 120 60 120
2 2
Max +80 +120 150 200
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
fCP = 8 MHz fCP = 8 MHz
fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz
*1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". Note : AC ratings are for CLK synchronized mode.
35
MB90980 Series
* Internal shift clock mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
36
MB90980 Series
(5) Extended I/O Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCKSOT delay time Valid SINSCK SCKvalid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 -80 -120 100 200 tCP*2 4 tCP* 4 tCP* 60 120 60 120
2 2
Max + 80 + 120 150 200
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
fCP = 8 MHz fCP = 8 MHz
fCP = 8 MHz fCP = 8 MHz fCP = 8 MHz
*1 : CL is the load capacitance applied to pins for testing. *2 : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing". Notes : * AC ratings are for CLK synchronized mode. * Values on this table are target values.
37
MB90980 Series
* Internal shift clock mode
tSCYC
SCK
0.8 V tSLOV 2.4 V
2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
38
MB90980 Series
(6) Timer Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol tTIWH tTIWL Pin name TIN0, IN0, IN1, PWC0, PWC1 Conditions Value Min 4 tCP* Max Unit Remarks
Input pulse width
ns
* : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing".
TIN0 IN0, IN1 PWC0, PWC1
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(7) Timer Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter CLKTout change time PPG0 to PPG3 change time OUT0 to OUT3 change time Symbol tTO Pin name TOT0, PPG0 to PPG3, OUT0 to OUT3 Conditions Load conditions 80 pF Value Min 30 Max Unit Remarks
ns
CLK
0.7 VCC
TOUT PPG0 to PPG3 OUT0 to OUT3
0.7 VCC 0.3 VCC
tTO
39
MB90980 Series
(8) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter SCL clock frequency Hold time (repeated) START condition SDASCL "L" width of the SCL clock "H" width of the SCL clock Set-up time (repeated) START condition SCLSDA Data hold time SCLSDA Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT When power supply voltage of external pull-up resistance is 5.5 V fCP*1 20 MHz, R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 20 MHz, R = 1.6 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V fCP*1 > 20 MHz, R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V fCP*1 > 20 MHz, R = 1.6 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 5.5 V R = 1.3 k, C = 50 pF*2 When power supply voltage of external pull-up resistance is 3.6 V R = 1.6 k, C = 50 pF*2 Condition Standard-mode Min 0 4.0 4.7 4.0 4.7 0 Max 100 3.45*3 Unit kHz s s s s s
250
ns
Data set-up time SDASCL
tSUDAT
200
ns
Set-up time for STOP condition SCLSDA Bus free time between a STOP and START condition
tSUSTO
4.0
s
tBUS
4.7
s
*1 : fCP is internal operation clock frequency. Refer to " (1) Clock Timing". *2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *3 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. Note : VCC = VCC3 = VCC5
SDA tLOW SCL tSUDAT tHDSTA tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
40
MB90980 Series
(9) Trigger Input Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol tTRGH, tTRGL Pin name ADTG, IRQ0 to IRQ7 Conditions Value Min 5 tCP* 1 Max Unit ns s Remarks Normal operation Stop mode
* : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing".
IRQ0 to IRQ7 ADTG
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
(10) Up-down Counter Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter AIN input "H" pulse width AIN input "L" pulse width BIN input "H" pulse width BIN input "L" pulse width AINBIN rise time BINAIN fall time AINBIN rise time BINAIN rise time BINAIN rise time AINBIN fall time BINAIN rise time AINBIN rise time ZIN input "H" pulse width ZIN input "L" pulse width Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL ZIN0, ZIN1 AIN0, AIN1, BIN0, BIN1 Load conditions 80 pF Pin name Conditions Value Min 8 tCP* 8 tCP* 8 tCP* 8 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* 4 tCP* Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
* : tCP is internal operating clock cycle time. Refer to " (1) Clock Timing".
41
MB90980 Series
tAHL 0.8 VCC 0.8 VCC 0.2 VCC
tALL
AIN
0.2 VCC
tAUBU
tBUAD
tADBD
tBDAU
0.8 VCC
0.8 VCC 0.2 VCC tBHL tBLL 0.2 VCC
BIN
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
BIN
tBUAU
tAUBD
tBDAD
tADBU
0.8 VCC
AIN
0.2 VCC
0.8 VCC
0.8 VCC
ZIN
tZHL tZLL
0.2 VCC
0.2 VCC
42
MB90980 Series
5. A/D Converter Electrical Characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V AVRH, TA = -40 C to +85 C) Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels Symbol Pin name VOT VFST IAIN VAIN IA IAH IR IRH AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVCC AVRH AVRH AN0 to AN7 Value Min AVSS - 1.5 LSB AVRH - 3.5 LSB 3.68 *1 AVSS AVSS + 2.2 Typ AVSS + 0.5 LSB AVRH - 1.5 LSB 0.1 1.4 94 Max 10 3.0 2.5 1.9 AVSS + 2.5 LSB AVRH + 0.5 LSB 10 AVRH AVCC 3.5 5 *2 150 5* 4
2
Unit bit LSB LSB LSB mV mV s A V V mA A A A LSB
Remarks
*1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) .
43
MB90980 Series
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R
Analog input During sampling : ON
C
Comparator
Note: The values are reference values.
MB90982 MB90F983
R C 2.5 k (Max) 31.0 pF (Max) 1.9 k (Max) 25.0 pF (Max)
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. * The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k)
MB90F983 MB90982
20
(External impedance = 0 k to 100 k)
MB90F983 MB90982
100
External impedance [k]
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
External impedance [k]
90
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * About errors As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. Note : Concerning sampling time, and compare time When 3.6 V AVCC 2.7 V, then Sampling time : 1.92 s, compare time : 1.1 s Settings should ensure that actual values do not go below these values due to operating frequency changes. 44
MB90980 Series
* Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16-bit) programming time Program/Erase cycle Flash Memory Data hold time Average TA = + 85 C TA = + 25 C, VCC = 3.0 V Conditions Value Min 10000 10 Typ 1 7 16 Max 15 3600 Unit s s s cycle year * Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead
* : The value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
* Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator
Pull-up resistance 1 Damping resistance 1
X1
X0
X0A
X1A
Internal damping resistance 0
Damping resistance 2
C1 C3 C4
C2
In normal use : Internal damping resistance 1 : Typ 600 k Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4
* Sample use with external clock input
X0
MB90980 series
OPEN
X1
45
MB90980 Series
ORDERING INFORMATION
Model MB90F983 MB90982 Package 64-pin plastic LQFP (FPT-64P-M03) Remarks
46
MB90980 Series
PACKAGE DIMENSIONS
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 10.0 x 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g P-LFQFP64-10x10-0.50
(FPT-64P-M03)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
12.000.20(.472.008)SQ
* 10.000.10(.394.004)SQ
48 33
0.1450.055 (.006.002)
49
32
Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F64009S-c-5-8
Dimensions in mm (inches). Note: The values in parentheses are reference values
47
MB90980 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept.
F0604

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